The original diode-capacitor memory was proposed using tube diodes by A. W. Holt of the U.S. National Bureau of Standards as described in Tele-Tech & Electronic Industries, p. 85, November 1953. The original dynamic random access memory (DRAM) was the subject of U.S. Pat. No. 3,387,286, by R. H. Dennard entitled Field Effect Transistor Memory and issued Jun. 4, 1968. This latter type of memory has become ubiquitous in the computer industry, and many refinements to it have been proposed and developed.
The present floating cell semi-monolithic memory invention represents a DRAM design which is an improved alternative to the field effect transistor memory type of device, rather than an improvement based on or derived from the original field effect transistor memory design configuration. This design was originally disclosed to the U.S. Patent and Trademark Office in Disclosure Document No. 279072 received Apr. 12, 1991.
Field effect transistor memory DRAMs have been configured as computer memories by fabricating multiple DRAM integrated circuit dice which are typically interconnected by mounting the dice in separate integrated circuit packages such as the common dual-in-line-pack (DIP) and connecting the packages to one another on a printed circuit (PC) board, or by mounting the dice directly onto a hybrid substrate and connecting the dice to the substrate in the manner that the packaged dice were connected to the packages. These connection methods include gold ball and aluminum wedge wire bonding and flip chip bonding, for example.
The present invention provides an improved alternative to these prior interconnection methods by allowing what would have been internal portions of monolithic dice to be physically and electrically interconnected to one another in a manner which offers higher spatial density, higher yield of usable dice, and thus lower cost for a given total memory size.
Contemporary DRAMs use various techniques of substituting extra sub-blocks of memory which test good for other sub-blocks on a memory die which test bad. The nature of preferred embodiments of the present invention is such that it permits fault correction techniques which are not as practical in typical existing field effect transistor memory DRAM configurations.